For example, the mixer circuit used in frequency converters and demodulators, etc. is often made of a circuit known as a Gilbert cell. The Gilbert cell is a circuit inverted by Mr. Barry Gilbert.
FIG. 8 is a schematic circuit diagram illustrating the basic constitution of said Gilbert cell.
In FIG. 8, Q1–Q6 represent npn transistors; CC1 represents a constant current circuit; R1 and R2 represent resistors; T1, T1′, T2, T2′, To and To′ represent terminals.
The emitters of npn transistors Q1 and Q2 are connected to each other, and they are also connected to reference potential GND via constant current circuit CC1. The base of npn transistor Q1 is connected to terminal T1, and the base of npn transistor Q2 is connected to terminal T1′.
The emitters of npn transistors Q3 and Q4 are connected to each other, and, at the same time, they are also connected to the collector of npn transistor Q1. Also, the base of npn transistor Q3 is connected to terminal T2, and the base of npn transistor Q4 is connected to terminal T2′.
The emitters of npn transistors Q5 and Q6 are connected to each other, and, at the same time, they are also connected to the collector of npn transistor Q2. Also, the base of npn transistor Q5 is connected to terminal T2′, and the base of npn transistor Q6 is connected to terminal T2.
The collectors of npn transistors Q3 and Q5 are connected to each other and to terminal To, and, at the same time, they are also connected through resistor R1 to power source Vcc.
The collectors of npn transistors Q4 and Q6 are connected to each other and to terminal To′, and, at the same time, they are also connected through resistor R2 to power source Vcc.
Constant voltage V1 is input as an in-phase voltage to terminal T1 and terminal T1′, and signal v1 is input to them as a differential voltage.
Constant voltage V2 is input as an in-phase voltage to terminal T2 and terminal T2′, and signal v2 is input to them as a differential voltage.
In the Gilbert cell shown in FIG. 8 with said constitution, the following relationship is established between input differential voltages v1 and v2 and output differential voltage vo.
                              v          0                =                                            v              01                        -                          v              02                                =                                    tanh              ⁡                              (                                                      v                    1                                                        2                    ⁢                                          V                      T                                                                      )                                      ·                          tanh              ⁡                              (                                                      v                    2                                                        2                    ⁢                                          V                      T                                                                      )                                      ·                          I              0                        ·                          R              L                                                          (        1        )            
In Equation (1), RL represents the resistance values of resistors R1 and R2, and VT represents the thermal voltage of the npn transistor.
Thermal voltage VT is the following function of Boltzmann constant k, temperature T of the junction portion of the transistor, and electron charge q: VT=kT/q
For example, assuming that the junction temperature T is 300K., it is about 26 mV.
First of all, in Equation (1), when input differential voltage v1 and input differential voltage v2 are much smaller than said thermal voltage VT, that is, when |v12VT|<<1 and |v2/2VT|<<1, one hastan h(v1/2VT)≈v1/2VTtan h(v2/2VT)≈v2/2VT
Consequently, Equation (1) can be approximately rewritten as follows.
                              v          0                =                                            v              01                        -                          v              02                                =                                                    (                                                      v                    1                                                        2                    ⁢                                          V                      T                                                                      )                            ·                              (                                                      v                    2                                                        2                    ⁢                                          V                      T                                                                      )                            ·                              I                0                            ·                              R                L                                      =                                                                                I                    0                                    ·                                      R                    L                                                                    4                  ·                                                            (                                              V                        T                                            )                                        2                                                              ⁢                              (                                  v1                  ·                  v2                                )                                                                        (        2        )            
As can be seen from Equation (2), output differential voltage vo is proportional to the product of input differential voltage v1 and input differential voltage v2, that is, the Gilbert cell shown in FIG. 8 functions as a multiplier.
Also, for the Gilbert cell shown in FIG. 8, usually, one of the input signals is a small signal, while the other input signal is a large signal. Consequently, consider the case when |v12VT|>>1 and |v2/2VT|>>1.
First of all, when v2/2VT>>1, one hastan h(v2/2VT)≈1
Consequently, Equation (1) can be approximately rewritten as follows.
      v    0    =            (                                    I            0                    ·                      R            L                                    2          ⁢                      V            T                              )        ·          v      1      When v2/2VT>>−1  (3),When v2/2VT<<−1, one hastan h(v2/2VT)≈−1
Consequently, Equation (1) can be approximately rewritten as follows.
                              v          0                =                                                            -                                  (                                                                                    I                        0                                            ·                                              R                        L                                                                                    2                      ⁢                                              V                        T                                                                              )                                            ·                              v                1                                      ⁢                                                  ⁢                                          v                2                                            2                ⁢                                  V                  T                                                              ⪡                                    -              1                        ⁢                                                          (        4        )            when v2/2VT>>−1  (4).
As can be seen from Equations (3) and (4), the magnitude of output differential voltage vo is proportional to input differential voltage v1, and the sign of output differential voltage vo is inverted corresponding to the sign of input differential voltage v2. This is equivalent to multiplying output differential voltage vo with a value of “+1” or “−1”, depending on the sign of input differential voltage v2. Consequently, even in this case, the Gilbert cell shown in FIG. 8 still functions as a multiplier.
However, for said Gilbert cell shown in FIG. 8, there are the following problems.
For the Gilbert cell shown in FIG. 8, for example, when constant current source CC1 is made of a conventional current mirror circuit, the maximum amplitude ΔVomax of the output signal that can be taken from terminal To or To′ is as follows:ΔVomax≦Vcc−3VceHere, Vce represents the collector-emitter voltage of the npn transistor. In order for the transistor to operate in a unsaturated state with high stability, said collector-emitter voltage Vce usually should be about 1 V. For example, assuming that power source Vcc=5 V, collector-emitter voltage Vcc=1 V, the maximum amplitude of the output signal, ΔVomax, becomesΔVomax≦5−3×1=2 (V)
Under the same condition, assuming that power source Vcc=3V, one hasΔVomax≦3−3×1=0 (V)Consequently, when power source Vcc=3 V, the Gilbert cell cannot operate with a high stability.
Consequently, for the Gilbert cell circuit shown in FIG. 8, stable operation cannot be realized as a low-voltage circuit with a power source voltage of 3 V or lower. This is a problem. On the other hand, in recent years, an ever increasing demand for lowering of the voltage for semiconductor integrated circuits has existed. Consequently, a demand exists for development of a type of multiplier that can operate at a power source voltage lower than that of said Gilbert cell circuit.
In the prior art, circuits shown in FIGS. 9 and 10 have been proposed as multipliers that can work under a low voltage.
FIG. 9 is a circuit diagram illustrating an example of a conventional multiplier that can work at a power source voltage lower than that of the Gilbert cell.
The same part numbers are used for FIGS. 8 and 9. Also, Q1′ and Q2′ represent pnp transistors, and CC2–CC4 represent constant current circuits.
For the multiplier shown in FIG. 9, instead of the differential amplifier composed of npn transistors Q1 Q2 and constant current circuit CC1 shown in FIG. 8, a differential amplifier composed of pnp transistors Q1′, Q2′ and constant current circuit CC4 is set.
That is, the emitters of pnp transistors Q1′ and Q2′0 are connected to each other, and, at the same time, they are connected through constant current circuit CC4 to power source Vcc. The collector of pnp transistor Q1′ is connected to the emitters of npn transistor Q3 and npn transistor Q4 that are connected to each other, and its base is connected to terminal T2. The collector of pnp transistor Q2′ is connected to the emitters of npn transistors Q5 and Q6 that are connected to each other, and its base is connected to terminal T2′. Constant voltage V2 is input as an in-phase voltage to terminals T2 and T2′, and signal v2 is input as a differential voltage to these terminals.
Also, the emitters of npn transistors Q3 and Q4 that are connected to each other are connected through constant current circuit CC2 to reference voltage GND. The emitters of npn transistors Q5 and Q6 that are connected to each other are connected through constant current circuit CC3 to reference potential GND.
For the multiplier shown in FIG. 9 with the aforementioned constitution, when conventional current mirror circuits are used to form constant current circuits CC2 and CC3, the maximum amplitude of the output signal, ΔVomax, becomesΔVomax≦Vcc−2VceThe amplitude of the output signal is larger than that of the Gilbert cell shown in FIG. 8 by collector-emitter voltage Vce of one transistor. In other words, it can work with high stability at a power source voltage lower by this voltage than that needed for the Gilbert cell.
FIG. 10 is a circuit diagram illustrating another example of a conventional multiplier that can work at a power source voltage lower than that of the Gilbert cell.
The part numbers for FIG. 10 are the same as those for FIG. 9. Also, Q7 and Q8 represent npn transistors, CC7–CC9 represent constant current circuits, and CV1 and CV2 represent constant voltage circuits.
For the multiplier shown in FIG. 10, instead of the differential amplifier composed of pnp transistors Q1′, Q2′ and constant current circuit CC4 shown in FIG. 9, a differential amplifier composed of npn transistors Q7, Q8, and constant current circuits CC7–CC9 is set.
That is, the emitters of npn transistors Q7 and Q8 are connected to each other, and, at the same time, they are connected through constant current circuit CC7 to reference potential GND. The collector of npn transistor Q7 is connected through constant current circuit CC8 to power source Vcc, and its base is connected to terminal T2. The collector of npn transistor Q8 is connected through constant current circuit CC9 to power source Vcc, and its base is connected to terminal T2′. Constant voltage V2 is input as an in-phase voltage to terminals T2 and T2′, and signal v2 is input as a differential voltage to these terminals.
Also, the collector of npn transistor Q7 is connected through constant voltage circuit CV1 to the emitters of npn transistors Q3 and Q4 that are connected to each other and also through constant current circuit CC8 to power source Vcc. The collector of npn transistor Q8 is connected through constant voltage circuit CV2 to the emitters of npn transistors Q5 and Q6 that are connected to each other and also through constant current circuit CC9 to power source Vcc.
For the multiplier shown in FIG. 10 with the aforementioned constitution, when conventional current mirror circuits are used to form constant current circuits CC2 and CC3, the maximum amplitude of the output signal, ΔVomax, becomesΔVomax≦Vcc−2VceThe amplitude of the output signal is larger than that of the Gilbert cell shown in FIG. 8 by collector-emitter voltage Vce of one transistor. In other words, it can work with high stability at a power source voltage lower by this voltage than that needed for the Gilbert cell.
However, for the conventional low-voltage multipliers shown in FIGS. 9 and 10, there are the following problems.
For the multiplier shown in FIG. 9, it is necessary to use pnp transistors. Consequently, compared with the Gilbert cell that uses only npn transistors, the frequency characteristics are worse.
Also, for the multipliers shown in FIGS. 9 and 10, current sources have to be set on both the power source Vcc side and the reference potential GND side. Also, it is necessary for the two current values to be in agreement with each other at high precision. Consequently, a complex circuit has to be set. In addition, these multipliers have more constant current circuits and constant voltage circuits than the Gilbert cell shown in FIG. 8. Consequently, the circuit becomes complicated. This is undesired.
A general object of this invention is to solve the aforementioned problems of the conventional methods by providing a type of multiplier that has a constitution simpler than that of the prior art and can perform multiplication operation at a power source voltage lower than that of the Gilbert cell. Another general object of this invention is to provide a type of multiplier that can perform multiplication operation at a power source voltage lower than that of the Gilbert cell, without using pnp transistors.